Codesign – Another increase in R&D management complexity

17 Jun 2010 Sandeep Mehta

An article in Nikkei Electronics Asia describes a new trend in consumer electronics: Codesign Begins with Product Implementation.  Codesign is simultaneous development of different subsystems, features and manufacturing process of a product across suppliers leading to cost and performance optimization at a system level.

Digital consumer electronics manufacturers are beginning to adopt codesign in product implementation. They hope to achieve both improved performance and reduced cost by optimizing chips, packages and boards in toto. PC-class performance at the implementation cost of consumer electronics would mean competitiveness sufficient for the global marketplace. Codesign is being implemented full-scale in digital consumer electronics. Until now separate design tasks were optimized individually, but now codesign is being used to improve overall system optimization. This approach makes it possible to cut design margins to the limit and develop products delivering powerful functionality for minimal price. 

With increasing complexity and somewhat nascent processes for cross-cultural cross-organizational R&D management, this can be a very challenging task for managers.  Especially, the biggest bang-for-the-buck for codesign is if it is implemented during concept development phase.  That means that all the different organizations have to align their processes, tools and metrics during the entire R&D pipeline.

Codesign can be applied to a wide range of design phases, but the most important one is concept design. The design enjoys the greatest freedom in the initial design phase, and as a result this is there the greatest optimization is possible. Codesign is entering use now in the conceptual design phase of digital consumer electronics. 

Furthermore, communications between different organizations gets to be even more critical (and difficult). As the article explains with an example of consumer electronics design, not only does design / development need to be synchronized, but also the testing / evaluation as well.  Reliability analysis & risk assessment can also become a nightmare.

There are two axes in codesign, the first of which is the target of the codesign process. There are three targets involved here, namely the chip design and package design (handled by the semiconductor manufacturer), and the board design (handled by the set manufacturer). The second axis is the set of indices used for design evaluation, such as signal integrity† and power integrity†. These indices are essential guides in avoiding product problems, and the goal in codesign is to satisfy all of the simultaneously. 

 However, this trend is likely to not be a passing fad.  As competition becomes global and need to address developing market becomes even greater, innovation will likely move to system level from components.

Better Performance at Lower Cost Digital consumer electronics designers are being pressed to slash margins to the bone, delivering better performance than prior models at the same or lower cost. ‘It used to be that we could afford a little cost increase if the product was the smallest one in the world, for example, and we could utilize high-performance boards or components. Not any more. Even if we make the smallest one in the world, the key point now is how cheap the parts are,’ complains Makoto Suzuki, Chief Distinguished Engineer, General Manager, EDA Design Technology Solutions Dept., MONO-ZUKURI Technology Div., Production Group, Sony Corp. of Japan. In this situation, continuing the established approach of individual design optimization would result in excessively large margins, and a loss in product competitiveness.

2 thoughts on “Codesign – Another increase in R&D management complexity

  1. Hosting

    We are also looking to the next generation of programming models, researching new algorithms, and evaluating the need to rewrite our major multiphysics applications from scratch, to address software architecture complexities and better manage ever-increasing layers of hardware complexity.

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